SH7616 datasheet(231/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 205 of 906

REJ09B0292-0200

BAMRAL Bits 15 to 0—Break Address Mask A15 to A0 (BAMA15 to BAMA0): These bits

specify whether or not corresponding channel A break address bits 15 to 0 (BAA15 to BAA0) set

in BARAL are to be masked.

Bit 31 to 0:

BAMAn

Description

Channel A break address bit BAAn is included in break condition (Initial value)

Channel A break address bit BAAn is masked, and not included in condition

Note: n = 31 to 0

6.2.3

Break Bus Cycle Register A (BBRA)

Bit:

——

———

Initial value:

R/W:

RRR

Bit:

543

210

CPA1

CPA0

IDA1

IDA0

RWA1

RWA0

SZA1

SZA0

Initial value:

R/W:

R/W

Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets four channel A

break conditions: (1) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (2) instruction

fetch/data access, (3) read/write, and (4) operand size. BBRA is initialized to H'0000 by a power-

on reset; after a manual reset, its value is undefined.

Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 7 and 6—CPU/DMAC, E-DMAC Cycle Select A (CPA1, CPA0): These bits specify whether

a CPU cycle, or a DMAC or E-DMAC cycle, is to be selected as the bus cycle used as a channel A

break condition.

Bit 7:

CPA1

Bit 6:

CPA0

Description

Channel A user break interrupt is not generated

(Initial value)

CPU cycle is selected as user break condition

DMAC or E-DMAC cycle is selected as user break condition

CPU, DMAC, or E-DMAC cycle is selected as user break condition

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