SH7616 datasheet(235/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 209 of 906

REJ09B0292-0200

BAMRBL Bits 15 to 0—Break Address Mask B15 to B0 (BAMB15 to BAMB0): These bits

specify whether or not corresponding channel B break address bits 15 to 0 (BAB15 to BAB0) set

in BARBL are to be masked.

Bit 31 to 0:

BAMBn

Description

Channel B break address bit BABn is included in break condition (Initial value)

Channel B break address bit BABn is masked, and not included in condition

Note: n = 31 to 0

6.2.6

Break Bus Cycle Register B (BBRB)

Bit:

——

———

Initial value:

R/W:

RRR

Bit:

543

210

CPB1

CPB0

IDB1

IDB0

RWB1

RWB0

SZB1

SZB0

Initial value:

R/W:

R/W

Break bus cycle register B (BBRB) is a 16-bit readable/writable register that sets four channel B

break conditions: (1) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (2) instruction

fetch/data access, (3) read/write, and (4) operand size. BBRB is initialized to H'0000 by a power-

on reset; after a manual reset, its value is undefined.

Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 7 and 6—CPU/DMAC, E-DMAC Cycle Select B (CPB1, CPB0): These bits specify whether

a CPU cycle, or a DMAC or E-DMAC cycle, is to be selected as the bus cycle used as a channel B

break condition.

Bit 7:

CPB1

Bit 6:

CPB0

Description

Channel B user break interrupt is not generated

(Initial value)

CPU cycle is selected as user break condition

DMAC or E-DMAC cycle is selected as user break condition

CPU, DMAC, or E-DMAC cycle is selected as user break condition

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