Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7616 Datasheet(PDF) 237 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 237 Page - Renesas Technology Corp

Back Button SH7616 Datasheet HTML 233Page - Renesas Technology Corp SH7616 Datasheet HTML 234Page - Renesas Technology Corp SH7616 Datasheet HTML 235Page - Renesas Technology Corp SH7616 Datasheet HTML 236Page - Renesas Technology Corp SH7616 Datasheet HTML 237Page - Renesas Technology Corp SH7616 Datasheet HTML 238Page - Renesas Technology Corp SH7616 Datasheet HTML 239Page - Renesas Technology Corp SH7616 Datasheet HTML 240Page - Renesas Technology Corp SH7616 Datasheet HTML 241Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 237 / 935 page
background image
Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 211 of 906
REJ09B0292-0200
6.2.7
Break Address Register C (BARC)
BARCH
Bit:
15
14
13
12
11
10
9
8
BAC31
BAC30
BAC29
BAC28
BAC27
BAC26
BAC25
BAC24
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
76
543
210
BAC23
BAC22
BAC21
BAC20
BAC19
BAC18
BAC17
BAC16
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BARCL
Bit:
15
14
13
12
11
10
9
8
BAC15
BAC14
BAC13
BAC12
BAC11
BAC10
BAC9
BAC8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
76
543
210
BAC7
BAC6
BAC5
BAC4
BAC3
BAC2
BAC1
BAC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Break address register C (BARC) consists of two 16-bit readable/writable registers: break address
register CH (BARCH) and break address register CL (BARCL). BARCH specifies the upper half
(bits 31 to 16) of the address used as a channel C break condition, and BARCL specifies the lower
half (bits 15 to 0). The address bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYEC bit/XYSC bit in break bus cycle register C (BBRC).
When XYEC = 0, BAC31 to BAC0 specify the address. When XYEC = 1, the upper 16 bits
(BAC31 to BAC16) of BARC specify the X address bus, and the lower 16 bits (BAC15 to BAC0)
specify the Y address bus. BARCH and BARCL are initialized to H'0000 by a power-on reset;
after a manual reset, their values are undefined.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com