SH7616 datasheet(241/935 Pages) RENESAS

241 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 215 of 906

REJ09B0292-0200

BDRC Configuration

Upper 16 Bits

(BDC31 to BDC16)

Lower 16 Bits

(BDC15 to BDC0)

XYEC = 0

Data

Upper 16 bits of data bus

Lower 16 bits of data bus

XYEC = 1

X data

(when XYSC = 0)

X data

(XDB15 to XDB0)

—

Y data

(when XYSC = 1)

—

Y data

(YDB15 to YDB0)

6.2.10

Break Data Mask Register C (BDMRC)

BDMRCH

Bit:

BDMC31 BDMC30 BDMC29 BDMC28 BDMC27 BDMC26 BDMC25 BDMC24

Initial value:

R/W:

R/W

Bit:

543

210

BDMC23 BDMC22 BDMC21 BDMC20 BDMC19 BDMC18 BDMC17 BDMC16

Initial value:

R/W:

R/W

BDMRCL

Bit:

BDMC15 BDMC14 BDMC13 BDMC12 BDMC11 BDMC10 BDMC9 BDMC8

Initial value:

R/W:

R/W

Bit:

543

210

BDMC7 BDMC6 BDMC5 BDMC4 BDMC3 BDMC2 BDMC1 BDMC0

Initial value:

R/W:

R/W

Break data mask register C (BDMRC) consists of two 16-bit readable/writable registers: break

data mask register CH (BDMRCH) and break data mask register CL (BDMRCL). BDMRCH

specifies which bits of the break data set in BDRCH are to be masked, and BDMRCL specifies

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