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SH7616 Datasheet(PDF) 244 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 244 Page - Renesas Technology Corp

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Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 218 of 906
REJ09B0292-0200
6.2.12
Break Execution Times Register C (BETRC)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
ETRC11 ETRC10 ETRC9
ETRC8
Initial value:
00
000
000
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
Bit:
76
543
210
ETRC7
ETRC6
ETRC5
ETRC4
ETRC3
ETRC2
ETRC1
ETRC0
Initial value:
00
000
000
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When a channel C execution-times break condition is enabled (by setting the ETBEC bit in
BRCR), this 16-bit register specifies the number of times a channel C break condition occurs
before a user break interrupt is requested. The maximum value is 212 – 1 times. Each time a
channel C break condition occurs, the value in BETRC is decremented by 1. After the BETRC
value reaches H'0001, an interrupt is requested when a break condition next occurs.
As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprising no
more than three instructions, BETRC is not decremented by the occurrence of a break condition
for an instruction in such a repeat loop (see 4.6, When Exception Sources Are Not Accepted).
Bits 15 to 12 are always read as 0, and should only be written with 0.
BETRC is initialized to H'0000 by a power-on reset.



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