SH7616 datasheet(243/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 217 of 906

REJ09B0292-0200

6.2.11

Break Bus Cycle Register C (BBRC)

Bit:

——

———

—

XYEC

XYSC

Initial value:

R/W:

RRR

R/W

Bit:

543

210

CPC1

CPC0

IDC1

IDC0

RWC1

RWC0

SZC1

SZC0

Initial value:

R/W:

R/W

Break bus cycle register C (BBRC) is a 16-bit readable/writable register that sets five channel C

break conditions: (1) internal bus (C-bus, I-bus)/X memory bus/Y memory bus), (2) CPU

cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (3) instruction fetch/data access, (4) read/write,

and (5) operand size. BBRC is initialized to H'0000 by a power-on reset; after a manual reset, its

value is undefined.

Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.

Bit 9—X/Y Memory Bus Enable C (XYEC): Selects whether the X/Y bus is used as a channel C

break condition.

Bit 9: XYEC

Description

Cache bus or internal bus is selected as condition for channel C address/data

(Initial value)

X/Y bus is selected as condition for channel C address/data

Bit 8—X Bus/Y Bus Select C (XYSC): Selects whether the X bus or the Y bus is used as a

channel C break condition. This bit is valid only when bit XYEC = 1.

Bit 8: XYSC

Description

X bus is selected as channel C break condition

(Initial value)

Y bus is selected as channel C break condition

The configuration of bits 7 to 0 is the same as for BBRA.

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