SH7616 datasheet(247/935 Pages) RENESAS

Part #	SH7616

Description	32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PDF	935 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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247 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 221 of 906

REJ09B0292-0200

Break address mask register D (BAMRD) consists of two 16-bit readable/writable registers: break

address mask register DH (BAMRDH) and break address mask register DL (BAMRDL).

BAMRDH specifies which bits of the break address set in BARDH are to be masked, and

BAMRDL specifies which bits of the break address set in BARDL are to be masked. Operation

also depends on bits XYED and XYSD in BBRD as shown below.

BAMRD Configuration

Upper 16 Bits

(BAMD31 to BAMD16)

Lower 16 Bits

(BAMD15 to BAMD0)

XYED = 0

Address

Upper 16 bits maskable

Lower 16 bits maskable

XYED = 1

X address

(when XYSD = 0)

Maskable

—

Y address

(when XYSD = 1)

—

Maskable

Bit 31 to 0:

BAMDn

Description

Channel D break address bit BADn is included in break condition (Initial value)

Channel D break address bit BADn is masked, and not included in condition

Note: n = 31 to 0

SH7616 Datasheet(PDF) 247 Page - Renesas Technology Corp