SH7616 datasheet(249/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 223 of 906

REJ09B0292-0200

BDRD Configuration

Upper 16 Bits

(BDD31 to BDD16)

Lower 16 Bits

(BDD15 to BDD0)

XYED = 0

Data

Upper 16 bits of data bus

Lower 16 bits of data bus

XYED = 1

X data

(when XYSD = 0)

X data

(XDB15 to XDB0)

—

Y data

(when XYSD = 1)

—

Y data

(YDB15 to YDB0)

6.2.16

Break Data Mask Register D (BDMRD)

BDMRDH

Bit:

BDMD31 BDMD30 BDMD29 BDMD28 BDMD27 BDMD26 BDMD25 BDMD24

Initial value:

R/W:

R/W

Bit:

543

210

BDMD23 BDMD22 BDMD21 BDMD20 BDMD19 BDMD18 BDMD17 BDMD16

Initial value:

R/W:

R/W

BDMRDL

Bit:

BDMD15 BDMD14 BDMD13 BDMD12 BDMD11 BDMD10 BDMD9 BDMD8

Initial value:

R/W:

R/W

Bit:

543

210

BDMD7 BDMD6 BDMD5 BDMD4 BDMD3 BDMD2 BDMD1 BDMD0

Initial value:

R/W:

R/W

Break data mask register D (BDMRD) consists of two 16-bit readable/writable registers: break

data mask register DH (BDMRDH) and break data mask register DL (BDMRDL). BDMRDH

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