Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7616 Datasheet(PDF) 252 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 252 Page - Renesas Technology Corp

Back Button SH7616 Datasheet HTML 248Page - Renesas Technology Corp SH7616 Datasheet HTML 249Page - Renesas Technology Corp SH7616 Datasheet HTML 250Page - Renesas Technology Corp SH7616 Datasheet HTML 251Page - Renesas Technology Corp SH7616 Datasheet HTML 252Page - Renesas Technology Corp SH7616 Datasheet HTML 253Page - Renesas Technology Corp SH7616 Datasheet HTML 254Page - Renesas Technology Corp SH7616 Datasheet HTML 255Page - Renesas Technology Corp SH7616 Datasheet HTML 256Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 252 / 935 page
background image
Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 226 of 906
REJ09B0292-0200
6.2.18
Break Execution Times Register D (BETRD)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
ETRD11 ETRD10 ETRD9
ETRD8
Initial value:
00
000
000
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
Bit:
76
543
210
ETRD7
ETRD6
ETRD5
ETRD4
ETRD3
ETRD2
ETRD1
ETRD0
Initial value:
00
000
000
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When a channel D execution-times break condition is enabled (by setting the ETBED bit in
BRCR), this 16-bit register specifies the number of times a channel D break condition occurs
before a user break interrupt is requested. The maximum value is 212 – 1 times. Each time a
channel D break condition occurs, the value in BETRD is decremented by 1. After the BETRD
value reaches H'0001, an interrupt is requested when a break condition next occurs.
As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprising no
more than three instructions, BETRD is not decremented by the occurrence of a break condition
for an instruction in such a repeat loop (see 4.6, When Exception Sources Are Not Accepted).
Bits 15 to 12 are always read as 0, and should only be written with 0.
BETRD is initialized to H'0000 by a power-on reset.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com