SH7616 datasheet(253/935 Pages) RENESAS

253 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 227 of 906

REJ09B0292-0200

6.2.19

Break Control Register (BRCR)

BRCRH

Bit:

CMFCA CMFPA

—

PCTE

PCBA

—

Initial value:

R/W:

R/W

Bit:

CMFCB CMFPB

—

SEQ1

SEQ0

PCBB

—

Initial value:

R/W:

R/W

BRCRL

Bit:

CMFCC CMFPC ETBEC

—

DBEC

PCBC

—

Initial value:

R/W:

R/W

Bit:

543

210

CMFCD CMFPD ETBED

—

DBED

PCBD

—

Initial value:

R/W:

R/W

The break control register (BRCR) is used to make the following settings:

1. Setting of independent channel mode or sequential condition mode for channels A, B, C, and D

2. Selection of pre- or post-instruction-execution break in case of an instruction fetch cycle

3. Selection of whether the data bus is to be included in the comparison conditions for channels C

and D

4. Selection of whether an execution-times break is to be set for channels C and D

5. Selection of whether a PC trace is to be executed

BRCR also contains flags that are set when a condition is satisfied. BRCR is initialized to

H'00000000 by a power-on reset; after a manual reset, its value is undefined.

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