SH7616 datasheet(254/935 Pages) RENESAS

254 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 228 of 906

REJ09B0292-0200

Bit 31—CPU Condition Match Flag A (CMFCA): This flag is set to 1 when a CPU bus cycle

condition, among the break conditions set for channel A, is satisfied. This flag is not cleared to 0

(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a

write).

Bit 31: CMFCA

Description

User break interrupt has not been generated by a channel A CPU cycle

condition

(Initial value)

User break interrupt has been generated by a channel A CPU cycle condition

Bit 30—DMAC Condition Match Flag A (CMFPA): This flag is set to 1 when an on-chip DMAC

bus cycle condition, among the break conditions set for channel A, is satisfied. This flag is not

cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be

cleared by a write).

Bit 30: CMFPA

Description

User break interrupt has not been generated by a channel A on-chip DMAC

cycle condition

(Initial value)

User break interrupt has been generated by a channel A on-chip DMAC cycle

condition

Bits 29 and 28—Reserved: These bits are always read as 0. The write value should always be 0.

Bit 27—PC Trace Enable (PCTE): Selects whether a PC trace is to be executed.

Bit 27: PCTE

Description

PC trace is not executed

(Initial value)

PC trace is executed

Bit 26—PC Break Select A (PCBA): Selects whether a channel A instruction fetch cycle break is

effected before or after execution of the instruction.

Bit 26: PCBA

Description

Channel A instruction fetch cycle break is effected before instruction execution

(Initial value)

Channel A instruction fetch cycle break is effected after instruction execution

Bits 25 and 24—Reserved: These bits are always read as 0. The write value should always be 0.

SH7616 Datasheet(PDF) 254 Page - Renesas Technology Corp