SH7616 datasheet(258/935 Pages) RENESAS

258 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 232 of 906

REJ09B0292-0200

Bit 5—Execution-Times Break Enable D (ETBED): Enables a channel D execution-times break

condition. When this bit is 1, a user break interrupt is generated when the number of break

conditions that have occurred equals the number of executions specified by the break execution

times register (BETRD).

Bit 5: ETBED

Description

Channel D execution-times break condition is disabled

(Initial value)

Channel D execution-times break condition is enabled

Bit 4—Reserved: This bit is always read as 0. The write value should always be 0.

Bit 3—Data Break Enable D (DBED): Selects whether a data bus condition is to be included in the

channel D break conditions.

Bit 3: DBED

Description

Data bus condition is not included in channel D conditions

(Initial value)

Data bus condition is included in channel D conditions

Bit 2—PC Break Select D (PCBD): Selects whether a channel D instruction fetch cycle break is

effected before or after execution of the instruction.

Bit 2: PCBD

Description

Channel D instruction fetch cycle break is effected before instruction execution

(Initial value)

Channel D instruction fetch cycle break is effected after instruction execution

Bits 1 and 0—Reserved: These bits are always read as 0. The write value should always be 0.

SH7616 Datasheet(PDF) 258 Page - Renesas Technology Corp