SH7616 datasheet(261/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 235 of 906

REJ09B0292-0200

The branch source registers (BRSR) comprise a set of four 32-bit read-only registers. The values

in these registers are used to calculate the address of the last instruction executed before a branch

when performing a PC trace. The BRSR registers form a FIFO (first-in first-out) queue for PC

trace use. The queue is shifted at each branch.

The BRSR registers are not initialized by a reset.

6.2.22

Branch Destination Registers (BRDR)

BRDRH

Bit:

BDA31

BDA30

BDA29

BDA28

BDA27

BDA26

BDA25

BDA24

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W:

RRRRRRRR

Bit:

BDA23

BDA22

BDA21

BDA20

BDA19

BDA18

BDA17

BDA16

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W:

RRRRRRRR

BRDRL

Bit:

BDA15

BDA14

BDA13

BDA12

BDA11

BDA10

BDA9

BDA8

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W:

RRRRRRRR

Bit:

76543210

BDA7

BDA6

BDA5

BDA4

BDA3

BDA2

BDA1

BDA0

Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

R/W:

RRRRRRRR

The branch destination registers (BRDR) comprise a set of four 32-bit read-only registers. These

registers store the branch destination fetch addresses used when performing a PC trace. The

BRDR registers form a FIFO (first-in first-out) queue for PC trace use. The queue is shifted at

each branch.

The BRDR registers are not initialized by a reset.

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