SH7616 datasheet(259/935 Pages) RENESAS

259 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 233 of 906

REJ09B0292-0200

6.2.20

Branch Flag Registers (BRFR)

Bit:

SVF

PID2

PID1

PID0

————

Initial value:

Undefined Undefined Undefined

0000

R/W:

RRRRRRRR

Bit:

76543210

DVF

———————

Initial value:

00000000

R/W:

RRRRRRRR

The branch flag registers (BRFR) comprise a set of four 16-bit read-only registers. The BRFR

registers contain flags indicating whether the actual branch addresses (in a branch instruction,

repeat, interrupt, etc.) have been saved in BRSR and BRDR, and a 3-bit pointer indicating the

number of cycles from fetch to execution of the last instruction executed. The BRFR registers

form a FIFO (first-in first-out) queue for PC trace use. The queue is shifted at each branch.

Bits SVF and DVF are initialized by a power-on reset, but bits PID2 to PID0 are not.

Bit 15—Source Verify Flag (SVF): Indicates whether the address and pointer that enable the

branch source address to be calculated have been stored in BRSR. This flag is set when the

instruction at the branch destination address is fetched, and reset when BRSR is read.

Bit 15: SVF

Description

BRSR value is invalid

(Initial value)

BRSR value is valid

Bits 14 to 12—PID2 to PID0: These bits comprise a pointer that indicates the instruction buffer

number of the instruction executed immediately before a branch occurred.

Bits 14 to 12:

PID2 to PID0

Description

Odd

PID indicates instruction buffer number

(Initial value)

Even

PID+2 indicates instruction buffer number

Bits 11 to 8, 6 to 0—Reserved: These bits are always read as 0. The write value should always be

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