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SH7616 Datasheet(PDF) 248 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 248 Page - Renesas Technology Corp |
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248 / 935 page  Section 6 User Break Controller (UBC) Rev. 2.00 Mar 09, 2006 page 222 of 906 REJ09B0292-0200 6.2.15 Break Data Register D (BDRD) BDRDH Bit: 15 14 13 12 11 10 9 8 BDD31 BDD30 BDD29 BDD28 BDD27 BDD26 BDD25 BDD24 Initial value: 00 000 000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 76 543 210 BDD23 BDD22 BDD21 BDD20 BDD19 BDD18 BDD17 BDD16 Initial value: 00 000 000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W BDRDL Bit: 15 14 13 12 11 10 9 8 BDD15 BDD14 BDD13 BDD12 BDD11 BDD10 BDD9 BDD8 Initial value: 00 000 000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 76 543 210 BDD7 BDD6 BDD5 BDD4 BDD3 BDD2 BDD1 BDD0 Initial value: 00 000 000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Break data register D (BDRD) consists of two 16-bit readable/writable registers: break data register DH (BDRDH) and break data register DL (BDRDL). BDRDH specifies the upper half (bits 31 to 16) of the data used as a channel D break condition, and BDRDL specifies the lower half (bits 15 to 0). The data bus connected to the X/Y memory can also be specified as a break condition by making a setting in the XYED bit/XYSD bit in break bus cycle register D (BBRD). When XYED = 1, the upper 16 bits (BDD31 to BDD16) of BDRD specify the X data bus, and the lower 16 bits (BDD15 to BDD0) specify the Y data bus. |
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