SH7616 datasheet(239/935 Pages) RENESAS

Part #	SH7616

Description	32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PDF	935 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

239 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 213 of 906

REJ09B0292-0200

Break address mask register C (BAMRC) consists of two 16-bit readable/writable registers: break

address mask register CH (BAMRCH) and break address mask register CL (BAMRCL).

BAMRCH specifies which bits of the break address set in BARCH are to be masked, and

BAMRCL specifies which bits of the break address set in BARCL are to be masked. Operation

also depends on bits XYEC and XYSC in BBRC as shown below.

BAMRC Configuration

Upper 16 Bits

(BAMC31 to BAMC16)

Lower 16 Bits

(BAMC15 to BAMC0)

XYEC = 0

Address

Upper 16 bits maskable

Lower 16 bits maskable

XYEC = 1

X address

(when XYSC = 0)

Maskable

—

Y address

(when XYSC = 1

—

Maskable

Bit 31 to 0:

BAMCn

Description

Channel C break address bit BACn is included in break condition (Initial value)

Channel C break address bit BACn is masked, and not included in condition

Note: n = 31 to 0

SH7616 Datasheet(PDF) 239 Page - Renesas Technology Corp