SH7616 datasheet(272/935 Pages) RENESAS

272 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 246 of 906

REJ09B0292-0200

After the instruction at address H'0000500 is executed, and the instruction at address

H'00000A00 is executed five times, a user break interrupt is generated after the instruction at

address H'00001000 has been executed nine times, but before it is executed a tenth time.

CPU Data Access Cycle Break Condition Settings

BARB = H'01000000 / BAMRB = H'00000000 / BBRB = H'0066

BARC = H'000ABCDE / BAMRC = H'000000FF / BBRC = H'006A

BDRC = H'0000A512 / BDMRC = H'00000000

BARD = H'1001E000 / BAMRD = H'FFFF0000 / BBRD = H'036A

BDRD = H'00004567 / BDMRD = H'00000000

BRCR = H'00000808

Set conditions:

All channels independent

Channel A: Address:

H'00123456; address mask: H'00000000

Bus cycle: CPU, data access, read (operand size not included

in conditions)

Channel B: Address:

H'01000000; address mask: H'00000000

Bus cycle: CPU, data access, read, word

Channel C: Address: H'000ABCDE; address mask: H'00000000

Data:

H'0000A512; data mask: H'00000000

Bus cycle: CPU, data access, write, word

Channel D: Y address: H'1001E000; address mask: H'FFFF0000

Data:

H'00004567; data mask: H'00000000

Bus cycle: CPU, data access, write, word

On channel A, a user break interrupt is generated by a longword read at address H'00123456, a

word read at address H'00123456, or a byte read at address H'00123456.

On channel B, a user break interrupt is generated by a word read at address H'01000000.

On channel C, a user break interrupt is generated when H'A512 is written by word access to an

address from H'000ABC00 to H'000ABCFE.

On channel D, a user break interrupt is generated when H'4567 is written by word access to

address H'1001E000 in Y memory space.

SH7616 Datasheet(PDF) 272 Page - Renesas Technology Corp