SH7616 datasheet(270/935 Pages) RENESAS

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Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 244 of 906

REJ09B0292-0200

B. Register settings: BARA = H'00027128 / BAMRA = H'00000000 / BBRA = H'005A

BARB = H'00031415 / BAMRB = H'00000000 / BBRB = H'0054

BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'0056

BDRC = H'00000000 / BDMRC = H'00000000

BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056

BDRD = H'00000000 / BDMRD = H'00000000

BRCR = H'00080000

Set conditions:

Channels A and B independent, channel C

→ channel D sequential mode

Channel A: Address:

H'00027128; address mask: H'00000000

Bus cycle: CPU, instruction fetch (pre-execution), write, word

Channel B: Address:

H'00031415; address mask: H'00000000

Bus cycle: CPU, instruction fetch (pre-execution),

read (operand size not included in conditions)

Channel C: Address:

H'00037226; address mask: H'00000000

Data:

H'00000000; data mask: H'00000000

Bus cycle: CPU, instruction fetch (pre-execution), read, word

Channel D: Address:

H'0003722E; address mask: H'00000000

Data:

H'00000000; data mask: H'00000000

Bus cycle: CPU, instruction fetch (pre-execution), read, word

On channel A, a user break interrupt is not generated as an instruction fetch is not a write

cycle.

On channel B, a user break interrupt is not generated as an instruction fetch is performed on an

even address.

A user break interrupt is generated by a channel C and D sequential condition match before

execution of the instruction at address H'0003722E following execution of the instruction at

address H'00037226.

C. Register settings: BBRA = H'0000

BBRB = H'0000

BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'005A

BDRC = H'00000000 / BDMRC = H'00000000

BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056

BDRD = H'00000000 / BDMRD = H'00000000

BRCR = H'00080000

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