SH7616 datasheet(273/935 Pages) RENESAS

273 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 247 of 906

REJ09B0292-0200

DMA Data Access Cycle Break Condition Settings

BBRB = H'0000

BBRC = H'0000

BARD = H'00055555 / BAMRD = H'00000000 / BBRD = H'00A9

BDRD = H'00007878 / BDMRD = H'00000F0F

BRCR = H'00000008

Set conditions:

All channels independent

Channel A: Address:

H'00314156; address mask: H'00000000

Bus cycle: DMAC, instruction fetch, read (operand not

included in conditions)

Channel B: Not used

Channel C: Not used

Channel D: Address:

H'00055555; address mask: H'00000000

Data:

H'00007878; data mask: H'00000F0F

Bus cycle: DMAC, data access, write, byte

On channel A, a user break interrupt is not generated as an instruction fetch is not performed in

a DMAC cycle.

On channel D, a user break interrupt is generated when the DMAC writes H'7* (*: Don't care)

is written by byte access to address H'00055555.

6.3.9

Usage Notes

1. UBC registers can be read and written to only by the CPU.

2. Note the following concerning sequential break specifications:

a. As the CPU has a pipeline structure, the order of instruction fetch cycles and memory

cycles is determined by the pipeline. Therefore, a break will occur if channel condition

matches in the bus cycle order satisfy the sequential condition.

b. If, of the channels included in a sequential condition, the channel bus cycle conditions

constituting the first break conditions of adjacent channels are specified as a pre-execution

break (PCB bit cleared to 0 in BRCR) and an instruction fetch (designated by the break bus

cycle register), note that when the bus cycle conditions for the two channels are matched

simultaneously, a break is effected and the BRCR condition match flags are set to 1.

SH7616 Datasheet(PDF) 273 Page - Renesas Technology Corp