SH7616 datasheet(269/935 Pages) RENESAS

269 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 243 of 906

REJ09B0292-0200

4. BRSR, BRDR, and BRFR have a four-queue structure. When the stored address is read in a PC

trace, the read is performed from the head of the queue. Reads should be performed in the

order BRFR, BRSR, BRDR. After BRDR is read, the queue shifts by one. Use longword

access to read BRSR and BRDR.

6.3.8

Examples of Use

CPU Instruction Fetch Cycle Break Condition Settings

A. Register settings: BARA = H'00000404 / BAMRA = H'00000000 / BBRA = H'0054

BARB = H'00003080 / BAMRB = H'0000007F / BBRB = H'0054

BARC = H'00008010 / BAMRC = H'00000006 / BBRC = H'0054

BDRC = H'00000000 / BDMRC = H'00000000

BARD =H'0000FF04 / BAMRD = H'00000000 / BBRD = H'0054

BDRD = H'00000000 / BDMRD = H'00000000

BRCR = H'04000400

Set conditions:

All channels independent

Channel A: Address:

H'00000404; address mask: H'00000000

Bus cycle: CPU, instruction fetch (post-execution),

read (operand size not included in conditions)

Channel B: Address:

H'00003080; address mask: H'0000007F

Bus cycle: CPU, instruction fetch (pre-execution),

read (operand size not included in conditions)

Channel C: Address:

H'00008010; address mask: H'00000006

Data:

H'00000000; data mask: H'00000000

Bus cycle: CPU, instruction fetch (post-execution),

read (operand size not included in conditions)

Channel D: Address:

H'0000FF04; address mask: H'00000000

Data:

H'00000000; data mask: H'00000000

Bus cycle: CPU, instruction fetch (pre-execution),

read (operand size not included in conditions)

A user break interrupt is generated after execution of the instruction at address H'00000404,

before execution of instructions at addresses H'00003080 to H'000030FF, after execution of

instructions at addresses H'00008010 to H'00008016, or before execution of the instruction at

address H'0000FF04.

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