SH7616 datasheet(268/935 Pages) RENESAS

268 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 242 of 906

REJ09B0292-0200

Exec:

Dest:

Int:

branch Dest

instr;

Not executed

Interrupt

interrupt routine

Figure 6.2 When Interrupt Occurs before Branch Instruction Is Executed

Table 6.3

BSA Values Stored in Exception Handling before Execution of Branch

Destination Instruction

Branch

Branch Destination

(Dest)

BSA

Branch Source Address Calculable by Means

of BRSR and BRFR

Delay

Exec = IA = BSA – 2

× PID

4n + 2

Dest = BSA

No delay

4n or 4n + 2

Exec = IA = BSA – 2

× PID

If PID is an odd number, the value incremented by 2 indicates the instruction buffer, but the

equations in the table do not take this into account. Therefore, the calculation can be performed

using the values of BSA stored in BRSR and PID stored in BRFR.

3. The location indicated by the address before branch occurrence, IA, differs according to the

kind of branch.

a. Branch instruction: Branch instruction address

b. Repeat loop: 2nd instruction from last in repeat loop

Repeat_Start: inst (1);

→ BRDR

inst(2);

inst (n-1);

→ Address calculated from BRSR and BRFR

Repeat End:

inst (n);

c. Interrupt: Instruction executed immediately before interrupt

The address of the first instruction in the interrupt routine is stored in BRDR.

In a repeat loop consisting of no more than three instructions, an instruction fetch cycle is not

generated. As the branch destination address is unknown, a PC trace cannot be performed.

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