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SH7616 Datasheet(PDF) 277 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 277 Page - Renesas Technology Corp |
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277 / 935 page ![]() Section 7 Bus State Controller (BSC) Rev. 2.00 Mar 09, 2006 page 251 of 906 REJ09B0292-0200 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the BSC. Area control unit MCR BSC RTCSR RTCNT RTCOR Comparator Memory control unit WCR1 WCR2 WCR3 Wait control unit WAIT CS4–CS0 BS STATS1, 0 RD CAS RAS RD/ WR WE3–WE0 CKE REFOUT IVECF Interrupt controller Bus interface WCR: Wait control register RTCSR: Refresh timer control/status register BCR: Bus control register RTCNT: Refresh timer counter MCR: Individual memory control register RTCOR: Refresh time constant register CMI interrupt request BCR1 BCR2 BCR3 Figure 7.1 BSC Block Diagram |
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