SH7616 datasheet(280/935 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 254 of 906

REJ09B0292-0200

7.1.4

The BSC has ten registers. These registers are used to control wait states, bus width, interfaces

with memories like DRAM, synchronous DRAM, and burst ROM, and DRAM and synchronous

DRAM refreshing. The register configurations are shown in table 7.2.

The size of the registers themselves is 16 bits. If read as 32 bits, the upper 16 bits are 0. In order to

prevent writing mistakes, 32-bit writes are accepted only when the value of the upper 16 bits of the

write data is H'A55A; no other writes are performed. Initialize the reserved bits.

Initialization Procedure: Do not access a space other than CS0 until the settings for the interface

to memory are completed.

Table 7.2

Name

Abbr.

R/W Initial Value Address*

Access Size

Bus control register 1

BCR1

R/W H'03F0

H'FFFFFFE0 16*

2, 32

Bus control register 2

BCR2

R/W H'00FC

H'FFFFFFE4 16*

2, 32

Bus control register 3

BCR3

R/W H'0F00

H'FFFFFFFC 16*

2, 32

Wait control register 1

WCR1

R/W H'AAFF

H'FFFFFFE8 16*

2, 32

Wait control register 2

WCR2

R/W H'000B

H'FFFFFFC0 16*

2, 32

Wait control register 3

WCR3

R/W H'0000

H'FFFFFFC4 16*

2, 32

Individual memory control register

MCR

R/W H'0000

H'FFFFFFEC 16*

2, 32

Refresh timer control/status register RTCSR

R/W H'0000

H'FFFFFFF0 16*

2, 32

Refresh timer counter

RTCNT

R/W H'0000

H'FFFFFFF4 16*

2, 32

Refresh time constant register

RTCOR

R/W H'0000

H'FFFFFFF8 16*

2, 32

Notes: 1. This address is for 32-bit accesses; for 16-bit accesses add 2.

2. 16-bit access is for read only.

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