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SH7616 Datasheet(PDF) 283 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 283 Page - Renesas Technology Corp |
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283 / 935 page ![]() Section 7 Bus State Controller (BSC) Rev. 2.00 Mar 09, 2006 page 257 of 906 REJ09B0292-0200 7.2 Register Descriptions 7.2.1 Bus Control Register 1 (BCR1) Bit: 15 14 13 12 11 10 9 8 — A4LW1 A4LW0 A2EN DIAN BST ROM —AHLW1 AHLW0 Initial value: 0 000001 1 R/W: R R/W R/W R/W R/W R R/W R/W Bit: 76543210 A1LW1 A1LW0 A0LW1 A0LW0 A4EN DIAN DRAM2 DRAM1 DRAM0 Initial value: 11110000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initialize the ENDIAN, BSTROM, PSHR, and DRAM2–DRAM0 bits after a power-on reset, and do not change their values thereafter. To change other bits by writing to them, write the same value as they are initialized to. Do not access any space other than CS0 until the register initialization ends. Bit 15—Reserved: This bit is always read as 0. The write value should always be 0. Bits 14 and 13—Long Wait Specification for Area 4 (A4LW1, A4LW0): From 3 to 14 wait cycles are inserted in CS4 space accesses when the wait control bits (W41, W40) in wait control register 2 (WCR2) are set as long wait (i.e., are set to 11) (see table 7.4). Bit 12—Endian Specification for Area 2 (A2ENDIAN): In big-endian format, the MSB of byte data is the lowest byte address and byte data goes in order toward the LSB . For little-endian format, the LSB of byte data is the lowest byte address and byte data goes in order toward the MSB . When this bit is 1, the data is rearranged into little-endian format before transfer when the CS2 space is read or written to. It is used when handling data with little-endian processors or running programs written with conscious use of little-endian format. Bit 12: A2ENDIAN Description 0 Big-endian (Initial value) 1 Little-endian |
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