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SH7616 Datasheet(PDF) 285 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 285 Page - Renesas Technology Corp |
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285 / 935 page ![]() Section 7 Bus State Controller (BSC) Rev. 2.00 Mar 09, 2006 page 259 of 906 REJ09B0292-0200 Bits 2 to 0—Enable for DRAM and Other Memory (DRAM2–DRAM0) DRAM2 DRAM1 DRAM0 Description 000CS2 and CS3 are ordinary spaces (Initial value) 1 CS2 is ordinary space; CS3 is synchronous DRAM space 1 0 CS2 is ordinary space; CS3 is DRAM space 1 Reserved (do not set) 100CS2 is synchronous DRAM space, CS3 is ordinary space 1 CS2 and CS3 are synchronous DRAM spaces 1 0 Reserved (do not set) 1 Reserved (do not set) Table 7.4 Wait Values Corresponding to BCR1 and BCR3 Register Settings (All Spaces) BCR3 BCR1 AnLW2 AnLW1 AnLW0 Wait Value 0 0 0 3 cycles inserted 1 4 cycles inserted 1 0 5 cycles inserted 1 6 cycles inserted 1 0 0 8 cycles inserted 1 10 cycles inserted 1 0 12 cycles inserted 1 14 cycles inserted (Initial value) Note: n = 0 to 4 AHLW2, AHLW1, and AHLW0 are common to CS2 and CS3. |
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