SH7616 datasheet(288/935 Pages) RENESAS

288 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 262 of 906

REJ09B0292-0200

Bits 11 to 8—Long Wait Specification for Areas 0 to 4 (AnLW2): When the basic memory

interface setting is made for CS n, from 3 to 14 wait cycles are inserted in CS n accesses,

according to the combination with the long wait specification bits (AnLW1 and AnLW0) in

BCR1, when the bits specifying the wait in the wait control register are set as long wait (i.e., are

set to 11). For a basic description of long waits, see section 7.2.1, Bus Control Register 1 (BCR1).

Bits 7 and 6—DMA Single-Write Wait (DSWW1, DSWW0): These bits determine the number of

wait states inserted between DACK assertion and

CASn assertion when writing to DRAM or EDO

RAM in DMA single address mode.

Bit 7: DSWW1

Bit 6: DSWW0

Description

0 waits

(Initial value)

11 wait

2 waits

Reserved (do not set)

Bits 5 to 3—Reserved bits: These bits are always read as 0. The write value should always be 0.

Bit 2—Number of Banks Specification when Using 64M Synchronous DRAM (BASEL): When

64M synchronous DRAM is specified by AMX2–AMX0 in MCR, the number of banks can be

specified.

Bit 2: BASEL

Description

4 banks

(Initial value)

2 banks

Bit 1—EDO Mode Specification (EDO): Enables EDO mode to be specified when DRAM is

specified for CS3 space.

Bit 1: EDO

Description

High-speed page mode

(Initial value)

EDO mode

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