SH7616 datasheet(291/935 Pages) RENESAS

291 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 265 of 906

REJ09B0292-0200

7.2.5

Wait Control Register 2 (WCR2)

Bit:

A4WD1 A4WD0

—

A4WM

A3WM

A2WM

A1WM

A0WM

Initial value:

00000000

R/W:

R/W

Bit:

76543210

————

IW41

IW40

W41

W40

Initial value:

00001011

R/W:

RRRR

R/W

Bits 15 and 14—Number of External Waits Specification for Area 4 (A4WD1, A4WD0): These

bits specify the number of cycles between acceptance of CS4 space external wait negation and

WEn negation.

Bit 15: A4WD1

Bit 14: A4WD0

Description

1 cycle

(Initial value)

2 cycles

4 cycles

Reserved (do not set)

Bit 13—Reserved bit. This bit is always read as 0. The write value should always be 0.

Bits 12 to 8—External Wait Mask Specification for Areas 0 to 4 (A4WM–A0WM): These bits

enable waits to be masked for CS spaces 0 to 4. When a value other than 00 is set in the wait

control bits for CS spaces 0 to 4 (W41–W00), external wait input can be enabled, but the wait

input can be masked by setting these bits to 1. With synchronous DRAM, external wait input is

ignored regardless of the settings.

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