SH7616 datasheet(294/935 Pages) RENESAS

294 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 268 of 906

REJ09B0292-0200

Bits 7 to 0—Area 3 to 0

CSn Assert Period Extension (A3SHW1–A0SHW0): These bits specify

the number of cycles from address/

CSn output to RD/WEn assertion and from RD/WEn negation

to address/

CSn hold for areas 3 to 0.

A3SHW1

A2SHW1

A1SHW1

A0SHW1

A3SHW0

A2SHW0

A1SHW0

A0SHW0

Description

0.5 cycle,

CSn* hold cycle = 0 cycles

(Initial value)

1.5 cycle,

CSn* hold cycle = 1 cycle

2.5 cycle,

CSn* hold cycle = 2 cycles

Reserved (do not set)

Note: * n = 0 to 3

7.2.7

Individual Memory Control Register (MCR)

Bit:

TRP0

RCD0

TRWL0 TRAS1

TRAS0

RASD

TRWL1

Initial value:

00000000

R/W:

R/W

Bit:

76543210

AMX2

AMX1

AMX0

RFSH

RMODE

TRP1

RCD1

Initial value:

00000000

R/W:

R/W

The TRP1–TRP0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, BE, RASD, AMX2–AMX0

and SZ bits are initialized after a power-on reset. Do not write to them thereafter. When writing to

them, write the same values as they are initialized to. Do not access CS2 or CS3 until register

initialization is completed.

Bits 1 and 15—

RAS Precharge Time (TRP1, TRP0): When DRAM is connected, specifies the

minimum number of cycles after

RAS is negated before the next assert. When synchronous

DRAM is connected, specifies the minimum number of cycles after precharge until a bank active

command is output. See section 7.5, Synchronous DRAM Interface, for details.

SH7616 Datasheet(PDF) 294 Page - Renesas Technology Corp

SH7616 Datasheet(HTML) 294 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL