SH7616 datasheet(296/935 Pages) RENESAS

296 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 270 of 906

REJ09B0292-0200

Bits 12 and 11—

CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits

specify the

RAS assertion width when DRAM is connected.

Bit 12: TRAS1

Bit 11: TRAS0

Description

2 cycles

(Initial value)

3 cycles

4 cycles

5 cycles

After an auto-refresh command is issued, a bank active command is not issued for TRAS cycles,

regardless of the TRP bit setting. For synchronous DRAM, there is no

RAS assertion period, but

there is a limit for the time from the issue of a refresh command until the next access. This value is

set to observe this limit. Commands are not issued for TRAS cycles when self-refresh is cleared.

Bit 12: TRAS1

Bit 11: TRAS0

Description

3 cycles

(Initial value)

4 cycles

6 cycles

9 cycles

Bit 10—Burst Enable (BE)

Bit 10: BE

Description

Burst disabled

(Initial value)

High-speed page mode during DRAM and ED0 interfacing is enabled

Burst access conditions are as follows:

• Longword access, cache fill access, or DMAC 16-byte transfer, with 16-bit

bus width

• Cache fill access or DMAC 16-byte transfer, with 32-bit bus width

During synchronous DRAM access, burst operation is always enabled

regardless of this bit

SH7616 Datasheet(PDF) 296 Page - Renesas Technology Corp