SH7616 datasheet(295/935 Pages) RENESAS

295 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 269 of 906

REJ09B0292-0200

• For DRAM interface

Bit 1: TRP1

Bit 15: TRP0

Description

1 cycle

(Initial value)

2 cycles

Reserved (do not set)

• For Synchronous DRAM interface

Bit 1: TRP1

Bit 15: TRP0

Description

1 cycle

(Initial value)

2 cycles

3 cycles

4 cycles

Bits 0 and 14—

RAS-CAS Delay (RCD1, RCD0): When DRAM is connected, specifies the

number of cycles after

RAS is asserted before CAS is asserted. When synchronous DRAM is

connected, specifies the number of cycles after a bank active (ACTV) command is issued until a

read or write command (READ, READA, WRIT, WRITA) is issued.

Bit 0: RCD1

Bit 14: RCD0

Description

1 cycle

(Initial value)

2 cycles

3 cycles

Reserved (do not set)

Bits 8 and 13—Write-Precharge Delay (TRWL1, TRWL0): When the synchronous DRAM is not

in the bank active mode, this bit specifies the number of cycles after the write cycle before the

start-up of the auto-precharge. Based on this number of cycles, the timing at which the next active

command can be issued is calculated within the bus controller. In bank active mode, this bit

specifies the number of cycles before the precharge command is issued after the write command is

issued. This bit is ignored when memory other than synchronous DRAM is connected.

Bit 8: TRWL1

Bit 13: TRWL0

Description

1 cycle

(Initial value)

2 cycles

3 cycles

Reserved (do not set)

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