SH7616 datasheet(293/935 Pages) RENESAS

293 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 267 of 906

REJ09B0292-0200

7.2.6

Wait Control Register 3 (WCR3)

Bit:

—

A4SW2 A4SW1 A4SW0

—

A4HW1 A4HW0

Initial value:

00000000

R/W:

R/W

Bit:

76543210

A3SHW1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0

Initial value:

00000000

R/W:

R/W

Bits 15 and 14—Reserved bits: These bits are always read as 0. The write value should always be

Bits 13 to 11—CS4 Address/

CS4 to RD/WEn Assertion (A4SW2–A4SW0): These bits specify the

number of cycles from address/

CS4 output to RD/WEn assertion for the CS4 space.

Bit 13: A4SW2

Bit 12: A4SW1

Bit 11: A4SW0

Description

0.5 cycles

(Initial value)

1.5 cycles

3.5 cycles

5.5 cycles

07.5 cycles

Reserved (do not set)

Bit 10—Reserved bit: This bit is always read as 0. The write value should always be 0.

Bits 9 and 8—Area 4

RD/WEn Negation to Address/CS4 Hold (A4HW1, A4HW0): These bits

specify the number of cycles from

RD/WEn negation to address/CS4 hold for the CS4 space.

Bit 9: A4HW1

Bit 8: A4HW0

Description

0.5 cycle,

CS4 hold cycle = 0 cycles

(Initial value)

1.5 cycle,

CS4 hold cycle = 1 cycle

3.5 cycle,

CS4 hold cycle = 3 cycles

5.5 cycle,

CS4 hold cycle = 5 cycles

SH7616 Datasheet(PDF) 293 Page - Renesas Technology Corp

SH7616 Datasheet(HTML) 293 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL