SH7616 datasheet(289/935 Pages) RENESAS

289 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 263 of 906

REJ09B0292-0200

Bit 0—Synchronous DRAM Burst Write Specification (BWE): Enables burst write mode to be

specified when synchronous DRAM is specified for CS2 or CS3 space.

Bit 0: BWE

Description

Single write mode

(Initial value)

Burst write mode

7.2.4

Wait Control Register 1 (WCR1)

Bit:

IW31

IW30

IW21

IW20

IW11

IW10

IW01

IW00

Initial value:

10101010

R/W:

R/W

Bit:

76543210

W31

W30

W21

W20

W11

W10

W01

W00

Initial value:

11111111

R/W:

R/W

Do not access a space other than CS0 until the settings for register initialization are completed.

Bits 15 to 8—Idles between Cycles for Areas 3 to 0 (IW31–IW00): These bits specify idle cycles

inserted between consecutive accesses to different CS spaces. Idles are used to prevent data

conflict between ROM or the like, which is slow to turn the read buffer off, and fast memories and

I/O interfaces. Even when access is to the same space, idle cycles must be inserted when a read

access is followed immediately by a write access. The idle cycles to be inserted comply with the

specification for the previously accessed space

. The set values below show the minimum number

of idle cycles; more cycles than indicated by the Idles between Cycles setting may actually be

inserted.

IW31, IW21, IW11, IW01

IW30, IW20, IW10, IW00

Description

No idle cycle

One idle cycle inserted

Two idle cycles inserted

(Initial value)

Four idle cycles inserted

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