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SH7616 Datasheet(PDF) 290 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 290 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev. 2.00 Mar 09, 2006 page 264 of 906
REJ09B0292-0200
Bits 7 to 0—Wait Control for Areas 3 to 0 (W31–W00)
• When the CSn space is set as ordinary space, the number of CSn space waits can be specified
with Wn1 and Wn0.
W31, W21,
W11, W01
W30, W20,
W10, W00
Description
0
0
External wait input disabled without wait
1
External wait input enabled with one wait
1
0
External wait input enabled with two waits
1
Complies with the long wait specification of bus control
register 1, 3 (BCR1, BCR3). External wait input is enabled
(Initial value)
• When CS3 is DRAM, the number of CAS assert cycles is specified by wait control bits W31
and W30
Bit 7: W31
Bit 6: W30
Description
0
0
1 cycle
1
2 cycles
1
0
3 cycles
1
Reserved (do not set)
When external wait mask bit A3WM in WCR2 is 0 and the number of
CAS assert cycles is set
to 2 or more, external wait input is enabled.
• When CS2 or CS3 is synchronous DRAM, CAS latency is specified by wait control bits W31
and W30, and W21 and W20, respectively
W31, W21
W30, W20
Description
0
0
1 cycle
1
2 cycles
1
0
3 cycles
1
4 cycles
(Initial value)
With synchronous DRAM, external wait input is ignored regardless of any setting.



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