SH7616 datasheet(284/935 Pages) RENESAS

284 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 258 of 906

REJ09B0292-0200

Bit 11—Area 0 Burst ROM Enable (BSTROM)

Bit 11: BSTROM

Description

Area 0 is accessed normally

(Initial value)

Area 0 is accessed as burst ROM

Bit 10—Reserved: This bit is always read as 0. The write value should always be 0.

Bits 9 and 8—Long Wait Specification for Areas 2 and 3 (AHLW1, AHLW0): When the basic

memory interface setting is made for CS2 and CS3, from 3 to 14 wait cycles are inserted in CS2 or

CS3 accesses when the bits specifying the respective area waits in the wait control bits (W21,

W20 or W31, W30) in wait control register 1 (WCR1) are set as long waits (i.e., are set to 11) (see

table 7.4).

Bits 7 and 6—Long Wait Specification for Area 1 (A1LW1, A1LW0): From 3 to 14 wait cycles

are inserted in area 1 accesses when the wait control bits (W11, W10) in wait control register 1

(WCR1) are set as long wait (i.e., are set to 11) (see table 7.4).

Bits 5 and 4—Long Wait Specification for Area 0 (A0LW1, A0LW0): When the basic memory

interface setting is made for CS0, from 3 to 14 wait cycles are inserted in CS0 accesses when the

wait control bits (W01, W00) in wait control register 1 (WCR1) are set as long wait (i.e., are set to

11) (see table 7.4).

Bit 3—Endian Specification for Area 4 (A4ENDIAN): In big-endian mode, the most significant

byte (MSB) is the lowest byte address, and byte data is aligned in order toward the least significant

byte (LSB). In little-endian mode, the LSB is the lowest byte address, and byte data is aligned in

order toward the MSB. When this bit is set to 1, data in read/write accesses to the CS4 space is

rearranged into little endian order before being transferred. This is used for data exchange with a

little-endian processor or when executing a program written with awareness of little-endian mode.

Bit 3: A4ENDIAN

Description

Big endian

(Initial value)

Little endian

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