SH7616 datasheet(278/935 Pages) RENESAS

278 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 252 of 906

REJ09B0292-0200

7.1.3

Pin Configuration

Table 7.1 shows the BSC pin configuration.

Table 7.1

Pin Configuration

Signal

I/O

With Bus

Released

Description

A24–A0

Hi-Z

Address bus. 32 Mbytes of memory space can be specified with 25

bits

D31–D0

I/O

Hi-Z

32-bit data bus. When reading or writing a 16-bit width area, use

D15–D0; when reading or writing a 8-bit width area, use D7–D0.

With 8-bit accesses that read or write a 32-bit width area, input and

output the data via the byte position determined by the lower

address bits of the 32-bit bus

Hi-Z

Indicates start of bus cycle or monitor. With the basic interface

(device interfaces except for DRAM, synchronous DRAM), signal is

asserted for a single clock cycle simultaneous with address output.

The start of the bus cycle can be determined by this signal

CS0–CS4 OHi-Z

Chip select.

CS3 is not asserted when the CS3 space is DRAM

space

RD/

Hi-Z

Read/write signal. Signal that indicates access cycle direction

(read/write). Connected to

WE pin when DRAM/synchronous

DRAM is connected

RAS

OHi-Z

RAS pin for DRAM/synchronous DRAM

CAS/OE

Hi-Z

Open when using DRAM

Connected to

OE pin when using EDO RAM

Connected to

CAS pin when using synchronous DRAM

Hi-Z

Read pulse signal (read data output enable signal). Normally,

connected to the device’s

OE pin; when there is an external data

buffer, the read cycle data can only be output when this signal is

low

WAIT

Don’t care

Hardware wait input

BRLS

Bus release request input

BGR

Bus grant output

CKE

Synchronous DRAM clock enable control. Signal for supporting

synchronous DRAM self-refresh

IVECF

Interrupt vector fetch

DREQ0

DMA request 0

DACK0

DMA acknowledge 0

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