SH7616 datasheet(332/935 Pages) RENESAS

332 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 306 of 906

REJ09B0292-0200

Tc1

CKIO

A24–A11

A10

A9–A1

CS2 or CS3

RAS

CAS

RD/

DQMxx

D31–D0

DACKn*

Tc2

Tc3

Tc4

Trwl

Tap

Tde

Note: * DACKn waveform when active-low is specified.

Figure 7.26 (b) Basic Burst Write Timing (Auto-Precharge) I

φφφφ : Eφφφφ = 1 : 1

7.5.7

Bank Active Function

A synchronous DRAM bank function is used to support high-speed accesses of the same row

address. When the RASD bit in MCR is set to 1, read/write accesses are performed using

commands without auto-precharge (READ, WRIT). In this case, even when the access is

completed, no precharge is performed. This function is not supported in the CS2 space. When the

bank active function is used, no precharge is performed when the access is completed. When

accessing the same row address in the same bank, a READ or WRIT command can be called

immediately without calling an ACTV command, just like the

RAS down mode of the DRAM’s

high-speed page mode

. Synchronous DRAM is divided into two banks, so one row address in each

can stay active. When the next access is to a different row address, a PRE command is called first

to precharge the bank, and access is performed by an ACTV command and READ or WRIT

command in order, after the precharge is completed. With successive accesses to different row

SH7616 Datasheet(PDF) 332 Page - Renesas Technology Corp