SH7616 datasheet(329/935 Pages) RENESAS

329 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 303 of 906

REJ09B0292-0200

CKIO

A24–A11

A10

A9–A1

CS2 or CS3

RAS

CAS

RD/

DQMxx

D31–D0

DACKn*

Td1

Td2

Td3

Td4

Tde

Tap

Note: * DACKn waveform when active-low is specified.

Figure 7.24 (b) Single Read Timing (Auto-Precharge) I

φφφφ : Eφφφφ = 1 : 1

7.5.5

Single Writes

Synchronous DRAM writes are executed as single writes or burst writes according to the

specification by the BWE bit in BCR3. Figure 7.25 shows the basic timing chart for single write

accesses. After the ACTV command Tr, a WRITA command is issued in Tc to perform an auto-

precharge. In the write cycle, the write data is output simultaneously with the write command.

When writing with an auto-precharge, the bank is precharged after the completion of the write

command within the synchronous DRAM, so no command can be issued to that bank until the

precharge is completed. For that reason, besides a Tap cycle to wait for the precharge during read

accesses, a Trw1 cycle is added to wait until the precharge is started, and the issuing of any new

commands to the same bank is delayed during this period. The number of cycles in the Trw1 cycle

can be specified using the TRWL1 and TRWL0 bits in MCR.

SH7616 Datasheet(PDF) 329 Page - Renesas Technology Corp