SH7616 datasheet(333/935 Pages) RENESAS

333 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 307 of 906

REJ09B0292-0200

addresses, the precharge is performed after the access request occurs, so the access time is longer.

When writing, performing an auto-precharge means that no command can be called for tRWL +

tAP cycles after a WRITA command is called. When the bank active mode is used, READ or

WRIT commands can be issued consecutively if the row address is the same. This shortens the

number of cycles by tRWL + tAP for each write. The number of cycles between the issue of the

precharge command and the row address strobe command is determined by the TRP1, TRP0 in

MCR.

Whether execution is faster when the bank active mode is used or when basic access is used is

determined by the proportion of accesses to the same row address (P1) and the average number of

cycles from the end of one access to the next access (tA). When tA is longer than tAP, the delay

waiting for the precharge during a read becomes invisible. If tA is longer than tRWL + tAP, the

delay waiting for the precharge also becomes invisible during writes. The difference between the

bank active mode and basic access speeds in these cases is the number of cycles between the start

of access and the issue of the read/write command: (tRP + tRCD)

× (1 – P1) and tRCD,

respectively.

The time that a bank can be kept active, tRAS, is limited. When the period will be provided by

program execution, and it is not assured that another row address will be accessed without a hit to

the cache, the synchronous DRAM must be set to auto-refresh and the refresh cycle must be set to

the maximum value tRAS or less. This enables the limit on the maximum active period for each

bank to be ensured. When auto-refresh is not being used, some measure must be taken in the

program to ensure that the bank does not stay active for longer than the prescribed period.

Figure 7.27 (a) and (b) show burst read cycles that is not an auto-precharge cycle, figure 7.28 (a)

and (b) show burst read cycles to a same row address, figure 7.29 (a) and (b) show burst read

cycles to different row addresses, figure 7.30 shows a write cycle without auto-precharge, figure

7.31 shows a write cycle to a same row address, and figure 7.32 shows a write cycle to different

row addresses.

In figure 7.28, a cycle that does nothing, Tnop, is inserted before the Tc cycle that issues the

READ command. Synchronous DRAMs have a 2 cycle latency during reads for the DQMxx

signals that specify bytes. If the Tc cycle is performed immediately without inserting a Tnop

cycle, the DQMxx signal for the Td1 cycle data output cannot be specified. This is why the Tnop

cycle is inserted. When the CAS latency is 2 or more, however, the Tnop cycle is not inserted so

that timing requirements will be met even when a DQMxx signal is set after the Tc cycle.

When the bank active mode is set, the access will start with figure 7.27 or figure 7.30 and repeat

figure 7.28 or figure 7.31 for as long as the same row address continues to be accessed when only

accesses to the respective banks of the CS3 space are considered. Accesses to other CS spaces

during this period do not affect this operation. When an access occurs to a different row address

while the bank is active, figure 7.29 or figure 7.32 will be substituted for figures 7.28 and 7.31

SH7616 Datasheet(PDF) 333 Page - Renesas Technology Corp