SH7616 datasheet(331/935 Pages) RENESAS

Part #	SH7616

Description	32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PDF	935 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 305 of 906

REJ09B0292-0200

Tap cycles can be set respectively in MCR by bits TRWL1 and TRWL0, and bits TRP1 and

TRP0.

When a single write is performed in burst write mode, the synchronous DRAM setting is for a

burst length of 4. After data is written in Tc1, empty writes are performed in Tc2, Tc3, and Tc4 by

driving the DQMxx signal high.

These empty cycles increase the memory access time and tend to reduce program execution speed

and DMA transfer speed. Therefore, unnecessary cache-through area accesses should be avoided,

and copy-back should be selected for the cache setting. Also, in DMA transfer, it is important to

use a data structure that allows transfer in 16-bit units.

Tc1

CKIO

A24–A11

A10

A9–A1

CS2 or CS3

RAS

CAS

RD/

DQMxx

D31–D0

DACKn*

Tc2

Tc3

Tc4

Trwl

Tap

Note: * DACKn waveform when active-low is specified.

Figure 7.26 (a) Basic Burst Write Timing (Auto-Precharge) I

φφφφ : Eφφφφ other than 1 : 1

SH7616 Datasheet(PDF) 331 Page - Renesas Technology Corp