 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS26521 Datasheet(PDF) 248 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
DS26521 Datasheet(HTML) 248 Page - Maxim Integrated Products |
|
|
248 / 258 page  DS26521 Single T1/E1/J1 Transceiver 248 of 258 12.2 JTAG Interface Timing Table 12-5. JTAG Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (See Figure 12-12.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock High:Low Time t2:t3 (Note 2) 50 500 ns JTCLK to JTDI, JTMS Setup Time t4 5 ns JTCLK to JTDI, JTMS Hold Time t5 2 ns JTCLK to JTDO Delay t6 2 50 ns JTCLK to JTDO High-Impendance Delay t7 2 50 ns JTRST Width Low Time t8 100 ns Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: Clock can be stopped high or low. Figure 12-12. JTAG Interface Timing Diagram JTCLK t1 JTD0 t4 t5 t2 t3 t7 JTDI, JTMS, JTRST t6 JTRST t8 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
