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AD9558 Datasheet(PDF) 41 Page - Analog Devices |
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AD9558 Datasheet(HTML) 41 Page - Analog Devices |
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41 / 104 page ![]() Data Sheet AD9558 Rev. A | Page 41 of 104 M3b DIVIDER/OUT5 PROGRAMMING IN FRAME SYNCHRONIZATION MODE In frame synchronization mode, the clock distribution signal path for OUT5 is changed, as follows: the OUT5 signal goes from the RF divider to the M0 divider, and then to the M3 and M3b dividers. This means that in frame synchronization mode, the total divide ratio between the RF divider and OUT5 is M0 × M3 × M3b. The other important change is that the sync signal for the M3b divider is no longer the standard clock distribution sync. It is controlled by a signal derived from the input frame pulse. OUPUT CLOCK (OUT0) FRAME CLOCK INPUT (REFC/REFD) ENABLE Fsync (REGISTER 0x0640[0] = 1b) FRAME SYNC ARM (REGISTER OR SYNC PIN) FRAME CLOCK (OUT5) ACTIVE SYNC ACTIVE SYNC NOTES 1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT. THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS A DELAY OF 0.5 TO 1.5 OUTPUT CLOCK CYCLES. Figure 41. Frame Synchronization in Level Sensitive Mode ACTIVE SYNC NOTES 1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT. THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS 0.5 TO 1.5 OUTPUT CLOCK CYCLES. OUPUT CLOCK (OUT0) FRAME CLOCK INPUT (REFC/REFD) ENABLE Fsync (REGISTER 0x0640[0] = 1b) FRAME SYNC ARM (REGISTER OR SYNC PIN) FRAME CLOCK (OUT5) Figure 42. Frame Synchronization in One Shot Mode FRAME SYNC PULSE INPUT (ON REFC OR REFD) Fsync_arm (FROM EITHER THE SYNC PIN OR THE Arm Soft Fsync BIT IN REGISTER 0x0641[0]) RF DIVIDER 1 CLOCK DISTRIBUTION SYNC LOGIC M3 DIVIDER M0 DIVIDER M3b DIVIDER FRAME SYNC PULSE GENERATOR ENABLE Fsync OUT0 OUT5 LOGIC 0 DELAY OUTPUT SYNC PULSE OUTPUT SYNC LEVEL (RETIMED) ENABLE Fsync ENABLE Fsync NOTES 1. THE ENABLE Fsync FUNCTION IN THE DIAGRAM IS CONTROLLED BY REGISTER 0x0640[0]. ENABLE Fsync FROM APLL Figure 43. Frame Synchronization Implementation |
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