AD9558 datasheet(97/104 Pages) AD

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Data Sheet

AD9558

Rev. A | Page 97 of 104

Table 112. Digital PLL Lock Detect Tub Levels1

Address

Bits

Bit Name

Description

0x0D11

[7:0]

Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Frequency Lock Detector

section for details.

0x0D12

[7:4]

Reserved.

[3:0]

Phase tub

Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Frequency Lock

Detector section for details.

0x0D13

[7:0]

Frequency tub

Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Phase Lock Detector

section for details.

0x0D14

[7:4]

Reserved

Reserved.

[3:0]

Frequency tub

Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Phase Lock Detector

section for details.

1These registers contain the current digital PLL lock detection bathtub levels.

EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)

Table 113. EEPROM Control

Address

Bits

Bit Name

Description

[7:1]

Reserved

Reserved.

0x0E00

Write enable

EEPROM write enable/protect.

0 (default) = EEPROM write protected.

1 = EEPROM write enabled.

[7:4]

Reserved

Reserved.

0x0E01

[3:0]

Conditional value

When set to a non-zero value, it establishes the condition for EEPROM downloads. Default: 0b.

[7:1]

Reserved

Reserved.

0x0E02

Save to EEPROM

Upload data to the EEPROM based on the EEPROM Storage Sequence (Register 0x0E10 to

[7:2]

Reserved

Reserved.

Load from EPROM

Downloads data from the EEPROM.

0x0E03

Reserved

Reserved.

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