AD9558 datasheet(18/104 Pages) AD

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AD9558

Data Sheet

Rev. A | Page 18 of 104

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT4

HSTL, LVDS, or

1.8 V CMOS

Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS.

OUT4

HSTL, LVDS,

or 1.8 V CMOS

Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

OUT3

HSTL, LVDS, or

1.8 V CMOS

Complementary Output 3. This output can be configured as HSTL, LVDS,

or single-ended 1.8 V CMOS.

OUT3

HSTL, LVDS, or

1.8 V CMOS

Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

OUT2

HSTL, LVDS, or

1.8 V CMOS

Complementary Output 2. This output can be configured as HSTL, LVDS, or

single-ended 1.8 V CMOS.

OUT2

HSTL, LVDS, or

1.8 V CMOS

Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

OUT1

HSTL, LVDS, or

1.8 V CMOS

Complementary Output 1. This output can be configured as HSTL, LVDS, or

single-ended 1.8 V CMOS.

OUT1

HSTL, LVDS,

or 1.8 V CMOS

Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

OUT5

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended

1.8 V or 3.3 V CMOS.

OUT5

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V

CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-

equivalent termination as described in the Input/Output Termination

Recommendations section.

25, 26

AVDD3

Power

3.3 V Analog (Output Driver) Power Supply.

OUT0

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Complementary Output 0. This output can be configured as HSTL, LVDS, or single-

ended 1.8 V or 3.3 V CMOS.

OUT0

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V

CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-

equivalent termination as described in the Input/Output Termination

Recommendations section.

AVDD3

Power

3.3V Analog (VCO 2) Power Supply.

LDO_VCO2

LDO bypass

Output PLL Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin

to ground. This pin is also the ac ground reference for the integrated output PLL

external loop filter.

LF_VCO2

I/O

Loop filter

Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this

pin to Pin 32 (LDO_VCO2).

No Connect. There is no internal connection for this pin.

AVDD

Power

1.8 V Analog (APLL) Power Supply.

No Connect. There is no internal connection for this pin.

37, 38

AVDD

Power

1.8 V Analog (DCO and TDC) Power Supplies.

RESET

3.3 V CMOS

Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has

an internal 50 kΩ pull-up resistor.

PINCONTROL

3.3 V CMOS

Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin

programming of the AD9558 configuration during startup. If this pin is low during

startup, the user must program the part via the serial port, or use values that are

stored in the EEPROM.

I/O

3.3 V CMOS

Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through

the AD9558 register space.

SYNC

3.3 V CMOS

Clock Distribution Synchronization Pin. When this pin is activated, output drivers are

held static and then synchronized on a low-to-high transition of this pin. This pin is

used to arm the frame sync function when frame sync mode is enabled and has an

internal 60 kΩ pull-up resistor.

AD9558 Datasheet(PDF) 18 Page - Analog Devices

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