AD9558 datasheet(65/104 Pages) AD

65 / 104 page

Data Sheet

AD9558

Rev. A | Page 65 of 104

Reg

Addr

(Hex)

Opt

Name

Def

Reference Inputs

0x0600

Reference

power-down

Reserved

Reference power-down[3:0]

0x0601

Reference

logic type

REFD logic type[1:0]

REFC logic type[1:0]

REFB logic type[1:0]

REFA logic type[1:0]

0x0602

Reference

priority

REFD priority[1:0]

REFC priority[1:0]

REFB priority[1:0]

REFA priority[1:0]

0x0603

Reserved

Frame Synchronization Mode

0x0640

En frame sync

Reserved

Enable Fsync

0x0641

Frame sync

options

Reserved

Validate

Fsync ref

Fsync one

shot

Fsync

arm

method

Arm soft Fsync

Profile A (for REFA)

0x0700

Reference

period (up to

1.1 ms)

Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting)

0x0701

Nominal period (fs), Bits[15:8]

0x0702

Nominal period (fs), Bits[23:16]

0x0703

Nominal period (fs), Bits[31:24]

0x0704

Nominal period (fs), Bits[39:32]

0x0705

Frequency

tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

0x0706

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

0x0707

Reserved

Inner tolerance, Bits[19:16]

0x0708

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%)

0x0709

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

0x070A

Reserved

Outer tolerance, Bits[19:16]

0x070B

Validation

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

0x070C

Validation timer (ms), Bits[15:8] (up to 65.5 seconds)

0x070D

Reserved

0x070E

Select base

loop filter

Reserved

Sel high PM

base loop

filter

0x070F

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

0x0710

Digital PLL loop BW scaling factor[15:8]

0x0711

Reserved

BW scaling

factor[16]

0x0712

DPLL

R divider

(20 bits)

R divider[7:0]

0x0713

R divider[15:8]

0x0714

Reserved

Enable REFA

divide-by-2

R divider[19:16]

0x0715

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

0x0716

Digital PLL feedback divider—Integer Part N1[15:8]

0x0717

Reserved

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x0718

DPLL

fractional

feedback

divider

(24 bits)

Digital PLL fractional feedback divider—FRAC1[7:0]

0x0719

Digital PLL fractional feedback divider—FRAC1[15:8]

0x071A

Digital PLL fractional feedback divider—FRAC1[23:16]

0x071B

DPLL

fractional

feedback

divider

modulus

(24 bits)

Digital PLL feedback divider modulus—MOD1[7:0]

0x071C

Digital PLL feedback divider modulus—MOD1[15:8]

0x071D

Digital PLL feedback divider modulus—MOD1[23:16]

0x071E

Lock detectors

Phase lock threshold (ps), Bits[7:0]

0x071F

Phase lock threshold (ps), Bits[15:8]

0x0720

Phase lock fill rate[7:0]

0x0721

Phase lock drain rate[7:0]

0x0722

Frequency lock threshold[7:0]

0x0723

Frequency lock threshold[15:8]

0x0724

Frequency lock threshold[23:16]

0x0725

Frequency lock fill rate[7:0]

0x0726

Frequency lock drain rate[7:0]

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