AD9558 datasheet(29/104 Pages) AD

29 / 104 page

Data Sheet

AD9558

Rev. A | Page 29 of 104

THEORY OF OPERATION

SPI/I2C

SERIAL PORT

EEPROM

REF MONITORING

AUTOMATIC

SWITCHING

÷N1

÷N2

÷N3

÷2

÷M1

OUT11

OUT21

MAX 1.25GHz

÷M2

×2

PFD/CP

DIVIDER 1

÷3 TO ÷11

XO OR XTAL

XO FREQUENCIES

10MHz TO 180MHz

XTAL: 10MHz TO 50MHz

DIVIDER 2

÷3 TO ÷11

FRAME SYNC PULSE

FRAME SYNC

MODE ONLY

OUTPUT PLL (APLL)

FRAC1/

MOD1

17-BIT

INTEGER

24b/24b

RESOLUTION

DIGITAL PLL (DPLL)

2kHz TO 8kHz FRAME SYNC SIGNAL

÷2

SPACE

R DIVIDER

(20-BIT)

SYNC

RESET

PINCONTROL

M0 M1 M2 M3

IRQ

SPI/I2C

DIGITAL

LOOP

FILTER

TUNING

WORD

CLAMP

AND

HISTORY

FREE RUN

APLL

STATUS

LF_VCO2

PFD/CP

DPFD

30-BIT

NCO

ROM

AND

FSM

MULTIFUNCTION I/O PINS

(CONTROL AND STATUS

READBACK)

SYSTEM

CLOCK

MULTIPLIER

M4 M5 M6 M7

÷2

AD9558

÷M0

÷M0 TO ÷M3b ARE

10-BIT INTEGER

DIVIDERS

1OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz

OUT0

OUT01

÷M3

OUT41

÷M3b

OUT51

×2

OUT31

REFC

REFD

÷2

REFA

REFB

3.35GHz

4.05GHz

Figure 35. Detailed Block Diagram

OVERVIEW

The AD9558 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference, but

with jitter characteristics that are governed by the system clock,

the DCO, and the output PLL (APLL). The AD9558 supports

up to four reference inputs and input frequencies ranging from

2 kHz to 1250 MHz. The core of this product is a digital phase-

locked loop (DPLL). The DPLL has a programmable digital loop

filter that greatly reduces jitter that is transferred from the active

reference to the output. The AD9558 supports both manual and

automatic holdover. While in holdover, the AD9558 continues to

provide an output as long as the system clock is present. The

holdover output frequency is a time average of the output

frequency history just prior to the transition to the holdover

condition. The device offers manual and automatic reference

switchover capability if the active reference is degraded or fails

completely. The AD9558 also has adaptive clocking capability

that allows the DPLL divider ratios to be changed while the DPLL

is locked.

The AD9558 has a system clock multiplier, a digital PLL (DPLL),

and an analog PLL (APLL). The input signal goes first to the DPLL,

which performs the jitter cleaning and most of the frequency

translation. The DPLL features a 30-bit digitally controlled

oscillator (DCO) output that generates a signal in the 175 MHz

to 200 MHz range. The DPLL output goes to an analog integer-N

PLL (APLL), which multiplies the signal up to the 3.35 GHz to

4.05 GHz range. That signal is then sent to the clock distribution

section, which has two divide-by-3 to divide-by-11 RF dividers

that are cascaded with 10-bit integer (divide-by-1 to divide-by-

1024) channel dividers.

The XOA and XOB pins provide the input for the system clock.

These pins accept a reference clock in the 10 MHz to 600 MHz

range, or a 10 MHz to 50 MHz crystal connected directly across

the XOA and XOB pins. The system clock provides the clocks to

the frequency monitors, the DPLL, and internal switching logic.

The AD9558 has six output drivers, arranged into four channels.

Each channel has a dedicated 10-bit programmable post divider.

Channel 0 and Channel 3 have one driver each, and Channel 1

and Channel 2 have two drivers each. Each driver is programmable

either as a single differential or dual single-ended CMOS output.

The clock distribution section operates at up to 1250 MHz.

In differential mode, the output drivers run on a 1.8 V power

supply to offer very high performance with minimal power

consumption. There are two differential modes: LVDS and 1.8 V

HSTL. In 1.8 V HSTL mode, the voltage swing is compatible

with LVPECL. If LVPECL signal levels are required, the designer

can ac-couple the AD9558 output and use Thevenin-equivalent

termination at the destination to drive the LVPECL inputs.

In single-ended mode, each differential output driver can

operate as two single-ended CMOS outputs. OUT0 and OUT5

support either 1.8 V or 3.3 V CMOS operation. OUT1 through

OUT4 support only 1.8 V operation.

AD9558 Datasheet(PDF) 29 Page - Analog Devices

AD9558 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL