AD9558 datasheet(84/104 Pages) AD

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AD9558

Data Sheet

Rev. A | Page 84 of 104

Table 73. Clock Distribution Channel 3 and OUT5 Driver Settings

Address

Bits

Bit Name

Description

Enable 3.3 V CMOS driver

0 (default) = disable 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x050F[6:4].

1 = enable 3.3 V CMOS driver as operating mode of OUT5.

This bit should be enabled only if Bits[6:4] are in CMOS mode.

[6:4]

OUT5 format

This control is valid when Register 0x050F[7] = 0; when Register 0x050F[7] = 1, OUT5 is in 3.3 V

CMOS mode and these bits are ignored.

Select the operating mode of OUT5.

000 = PD, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2]

OUT5 polarity

Control the OUT5 polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, negative.

OUT5 drive strength

Controls the output drive capability of OUT5.

0 (default) = CMOS: low drive strength, LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength, LVDS: 4.5 mA nominal (LVDS boost mode).

Note that this is only in 3.3 V CMOS mode for CMOS strength.

1.8 V CMOS has only the low drive strength.

0x050F

OUT5 enable

Enables/disables (1b/0b) OUT5 1.8 V driver (default is disabled).

This bit does not enable/disable OUT5 if Bit 7 of this register is set.

0x0510

[7:0]

Channel 3, Divider 1 (M3)

division ratio

10-bit channel divider, Bits[7:0] (LSB) (default: 0x03).

Division equals channel divider, Bits[9:0] + 1.

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024).

[7:2]

Reserved

Reserved.

0x0511

[1:0]

Channel 3, Divider 1 (M3)

division ratio

10-bit channel divider, Bits[9:8] (MSB) (default: 0x00).

0x0512

[7:0]

Channel 3, Divider 2

(M3b) division ratio

10-bit channel divider, Bits[7:0] (LSB).

Division equals channel divider bits[9:0] + 1 .

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024).

[7:4]

Reserved

Reserved.

Channel 3 doubler

0 (default) = normal operation.

1 = enables Channel 3 clock doubler. This bit activates an internal clock doubler that doubles

the frequency of the Channel 3 divider. In this mode, Channel 3, Divider 2 is bypassed.

PD Channel 3

0 (default) = normal operation.

1 = powers down Channel 3.

Select RF divider

for Channel 2

1 = selects RF Divider 2 as prescaler for the Channel 3 divider.

0 (default) = selects RF Divider 1 as a prescaler for the Channel 3 divider.

0x0513

[1:0]

Channel 3, Divider 2

(M3b) division ratio

10-bit channel divider, Bits[9:8] (MSB).

0x0514

[7:0]

Channel 3, Divider 1 (M3)

phase

The same control for Channel 3, Divider 1 phase as found in Register 0x0504 for Channel 0

divider phase (default: 0x00).

0x0515

[7:0]

Channel 3, Divider 2

(M3b) phase

The same control for Channel 3, Divider 2 phase as found in Register 0x0504 for Channel 0

divider phase (default: 0x00).

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