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AD9558

Data Sheet

Rev. A | Page 82 of 104

Table 68. Distribution OUT0 Setting

Address

Bits

Bit Name

Description

0x0501

Enable 3.3 V CMOS driver

0 (default) = disables 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x0501[6:4].

1 = enables 3.3 V CMOS driver as operating mode of OUT0.

This bit should be enabled only if Bits[6:4] are in CMOS mode.

[6:4]

OUT0 format

This control is valid when Register 0x0501[7] = 0.

When Register 0x0501[7] = 1, OUT5 is in 3.3 V CMOS mode and these bits are ignored.

Select the operating mode of OUT0.

000 = PD, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2]

OUT0 polarity

Control the OUT0 polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, nevative.

OUT0 drive strength

Controls the output drive capability of OUT0.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode).

Note that this is only in 3.3 V CMOS mode for CMOS strength.

1.8 V CMOS has only the low drive strength.

Enable OUT0

Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled).

This bit does not enable/disable OUT0 if Bit 7 of this register is set.

Table 69. Distribution Channel 0 Divider Setting

Address

Bits

Bit Name

Description

0x0502

[7:0]

Channel 0 (M0)

division ratio

10-bit channel divider bits[7:0] (LSB).

Division equals channel divider, Bits[9:0] + 1.

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024)

0x0503

[7:4]

Reserved

Reserved.

Channel 0 PD

0 (default) = normal operation.

1 = powers down Channel 0.

Select RF Divider 2

1 = selects RF Divider 2 as prescaler for Channel 0 divider.

0 (default) = selects RF Divider 1 as prescaler for Channel 0 divider.

[1:0]

Channel 0 (M0)

division ratio

10-bit channel divider, Bits[9:8] (MSB)

[7:6]

Reserved

Reserved. Default: 00b

0x0504

[5:0]

Channel 0 divider phase

Divider initial phase after sync relative to the divider input clock (from the RF divider

output). LSB is ½ of a period of the divider input clock. Default: 00000b.

Phase = 0 is no phase offset.

Phase = 1 is ½ a period offset.

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