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AD9558 Datasheet(PDF) 69 Page - Analog Devices |
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AD9558 Datasheet(HTML) 69 Page - Analog Devices |
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69 / 104 page  Data Sheet AD9558 Rev. A | Page 69 of 104 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def Operational Controls 0x0A00 Power-down Soft reset exclude regmap DCO PD SYSCLK PD Ref input PD TDC PD APLL PD Clock dist PD Full PD 00 0x0A01 Loop mode Reserved User holdover User freerun REF switchover mode[2:0] User ref in manual switchover mode 00 0x0A02 Cal/sync Reserved Soft sync clock dist Reserved 00 0x0A03 A Clear/reset functions Reserved Clear LF Clear CCI Reserved Clear auto sync Clear TW history Clear all IRQs Clear watchdog 00 0x0A04 A IRQ clearing Reserved Reserved SYSCLK unlocked SYSCLK locked APLL unlocked APLL locked APLL cal ended APLL cal started 00 0x0A05 A Reserved Pin program end Sync clock dist Watchdog timer EEPROM fault EEPROM complete 00 0x0A06 A Switching Closed Freerun Holdover Frequency unlocked Frequency locked Phase unlocked Phase locked 00 0x0A07 A Reserved History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited 00 0x0A08 A Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault 00 0x0A09 A Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault 00 0x0A0A A Increment phase offset Reserved Reset phase offset Decrement phase offset Increment phase offset 00 0x0A0B A Manual reference validation Reserved Force Timeout D Force Timeout C Force Timeout B Force Timeout A 00 0x0A0C Manual reference invalidation Reserved REF Mon Override D REF Mon Override C REF Mon Override B REF Mon Override A 00 0x0A0D Static reference validation Reserved REF Mon Bypass D REF Mon Bypass C REF Mon Bypass B REF Mon Bypass A 00 Quick In-Out Frequency Soft Pin Configuration 0x0C00 L, E Enable Soft Pin Section 1 Reserved En Soft Pin Section 1 00 0x0C01 L, E Soft Pin Section 1 Output frequency selection[3:0] Input frequency selection[3:0] 00 0x0C02 L, E Reserved SYSCLK PLL REF selection[1:0] 00 0x0C03 L, E Enable Soft Pin Section 2 Reserved En Soft Pin Section 2 00 0x0C04 L, E Soft Pin Section 2 REFD frequency scale[1:0] REFC frequency scale[1:0] REFB frequency scale[1:0] REFA frequency scale[1:0] 00 0x0C05 L, E Channel 3 output frequency scale[1:0] Channel 2 output frequency scale[1:0] Channel 1 output frequency scale[1:0] Channel 0 output frequency scale[1:0] 00 0x0C06 L, E Reserved Sel high PM base loop filter DPLL BW[1:0] REF tolerance[1:0] 00 0x0C07 L, A, E Reserved Soft pin start transfer 00 0x0C08 L, E Reserved Soft pin reset 00 |
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