AD9558 datasheet(90/104 Pages) AD

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AD9558

Data Sheet

Rev. A | Page 90 of 104

Reset Functions (Register 0x0A03)

Table 92. Reset Functions1

Address

Bits

Bit Name

Description

Reserved

Default: 0b.

Clear LF

Setting this bit clears the digital loop filter (intended as a debug tool).

Clear CCI

Setting this bit clears the CCI filter (intended as a debug tool).

Reserved

Default: 0b.

Clear auto sync

Setting this bit resets the automatic synchronization logic (see Register 0x0500).

Clear TW history

Setting this bit resets the tuning word history logic (part of holdover functionality).

Clear all IRQs

Setting this bit clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D07).

It is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to

0x0A03

(autoclear)

Clear watchdog timer

Setting this bit resets the watchdog timer (see Register 0x0211 and Register 0x0212). If the

timer times out, it starts a new timing cycle. If the timer has not yet timed out, it restarts at

time zero without causing a timeout event. Continuously resetting the watchdog timer at

intervals less than its timeout period prevents the watchdog timer from generating a timeout

event.

1 Note that all bits in this register are autoclearing.

IRQ Clearing (Register 0x0A04 to Register 0x0A09)

The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D02 to Register 0x0D09). When set to logic 1,

an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ

clearing register is an autoclearing register.

Table 93. IRQ Clearing for SYSCLK

Address

Bits

Bit Name

Description

[7:6]

Reserved

SYSCLK unlocked

Clears SYSCLK unlocked IRQ

SYSCLK locked

Clears SYSCLK locked IRQ

APLL unlocked

Clears Output PLL unlocked IRQ

APLL locked

Clears Output PLL locked IRQ

APLL Cal ended

Clears APLL calibration complete IRQ

0x0A04

APLL Cal started

Clears APLL calibration started IRQ

Table 94. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bits

Bit Name

Description

[7:5]

Reserved

Pin program end

Clears pin program end IRQ

Sync clock distribution

Clears distribution sync IRQ

Watchdog timer

Clears watchdog timer IRQ

EEPROM fault

Clears EEPROM fault IRQ

0x0A05

EEPROM complete

Clears EEPROM complete IRQ

Table 95. IRQ Clearing for the Digital PLL

Address

Bits

Bit Name

Description

Switching

Clears switching IRQ

Closed

Clears closed IRQ

Freerun

Clears free run IRQ

Holdover

Clears holdover IRQ

Frequency unlocked

Clears frequency unlocked IRQ

Frequency locked

Clears frequency locked IRQ

Phase unlocked

Clears phase unlocked IRQ

0x0A06

Phase locked

Clears phase locked IRQ

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