AD9558 datasheet(75/104 Pages) AD

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Data Sheet

AD9558

Rev. A | Page 75 of 104

IRQ MASK (REGISTER 0x020A TO REGISTER 0x020F)

The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D02 to 0x0D09). When set to

Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0,

which prevents the IRQ monitor from detecting any internal interrupts.

Table 48. IRQ Mask for SYSCLK

Address

Bits

Bit Name

Description

[7:6]

Reserved

SYSCLK unlocked

Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked

SYSCLK locked

Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked

APLL unlocked

Enables IRQ for indicating an APLL state transition from locked to unlocked

APLL locked

Enables IRQ for indicating an APLL state transition from unlocked to locked

APLL cal complete

Enables IRQ for indicating that APLL (LCVCO) calibration has completed

0x020A

APLL cal started

Enables IRQ for indicating that APLL (LCVCO) calibration has begun

Table 49. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bits

Bit Name

Description

[7:5]

Reserved

Pin program end

Enables IRQ for indicating successful completion of a pin program ROM load

Sync distribution

Enables IRQ for indicating a distribution sync event

Watchdog timer

Enables IRQ for indicating expiration of the watchdog timer

EEPROM fault

Enables IRQ for indicating a fault during an EEPROM load or save operation

0x020B

EEPROM complete

Enables IRQ for indicating successful completion of an EEPROM load or save operation

Table 50. IRQ Mask for the Digital PLL

Address

Bits

Bit Name

Description

Switching

Enables IRQ for indicating that the DPLL is switching to a new reference

Closed

Enables IRQ for indicating that the DPLL has entered closed-loop operation

Freerun

Enables IRQ for indicating that the DPLL has entered free run mode

Holdover

Enables IRQ for indicating that the DPLL has entered holdover mode

Frequency unlocked

Enables IRQ for indicating that the DPLL lost frequency lock

Frequency locked

Enables IRQ for indicating that the DPLL has acquired frequency lock

Phase unlocked

Enables IRQ for indicating that the DPLL lost phase lock

0x020C

Phase locked

Enables IRQ for indicating that the DPLL has acquired phase lock

Table 51. IRQ Mask for History Update, Frequency Limit and Phase Slew Limit

Address

Bits

Bit Name

Description

[7:5]

Reserved

History updated

Enables IRQ for indicating the occurrence of a tuning word history update

Frequency unclamped

Enables IRQ for indicating a frequency limit state transition from clamped to unclamped

Frequency clamped

Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped

Phase slew unlimited

Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not

slew limiting

0x020D

Phase slew limited

Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to

slew limiting

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